1. Field of the Invention
The present invention relates to a semiconductor device comprising a MOSFET chip having one surface on which a gate electrode and a source electrode are provided and other surface on which a drain electrode is provided, and more particularly, it relates to an improvement in the structure of the source electrode.
2. Description of the Prior Art
An ordinary power MOSFET chip has a lot of MOSFET elements being electrically interconnected in parallel.
FIG. 1 is a plane view of such a power MOSFET chip, and FIG. 2 is a cross section showing a schematical structure of the power MOSFET chip. The structure shown in FIG. 1 and FIG. 2 is common to power MOSFET chips 1a and 1b, since structures of the power MOSFET chips 1a and 1b are identical to each other. In order to distinguish the power MOSFET chip 1a from the power MOSFET chip 1b, components with respect to the chips 1a and 1b are referred by reference numerals having suffix "a" and "b", respectively.
Referring to FIGS. 1 and 2, an N.sup.- -type layer 13a (13b) is epitaxially grown on one major surface of an N.sup.+ -type semiconductor substrate 12a (12b). Impurities are selectively diffused from the surface of the N.sup.- -type layer 13a (13b) to form a plurality of P.sup.+ -type regions 14a (14b), while impurities are selectively diffused from the surface of each P.sup.+ -type region 14a (14b) to form a pair of N.sup.+ -type regions 15a (15b). As shown in FIG. 2, an insulation layer 16a (16b) is formed on the surfaces of the P.sup.+ -type regions 14a (14b) between the surface of the N.sup.- -type layer 13a (13b) and those of the N.sup.+ -type regions 15a (15b). The insulation layer 16a (16b) also covers the surface of the portion of the N.sup.+ -type regions 15a (15b) and the surface of the N.sup.- -type layer 13a (13b) between the P.sup.+ -type regions 14a (14b). A gate electrode 17a (17b ) of , e.g., polysilicon is formed into the insulation layer 16a (16b), while a source electrode 19a (19b) of metal such as aluminum is formed to be electrically connected to both of the P.sup.+ -type regions 14a (14b) and N.sup.+ -type regions 15a (15b). On the rear surface of the N.sup.+ -type semiconductor substrate 12a (12b), a metal drain electrode 18a (18b) is provided. The gate electrodes 17a (17b) are connected to a gate terminal 3a (3b) and the source electrode 19a (19b) is connected to a source terminal 2a (2b), while the drain electrode 18a (18b) is connected to a drain terminal 4a (4b) respectively.
FIG. 3 is a plane view showing the structure of a conventional semiconductor device having the power MOSFET chips 1a and 1b in a state that wire bonding processes are completed, and FIG. 4 is a cross section of the semiconductor device after an assembly process. As shown in FIG. 3, insulation layers 9a and 9b are formed on a substrate 5 of the semiconductor device to align with a constant interval. A source terminal 2a, a gate terminal 3a and a drain terminal 4a are provided on the insulation layer 9a, while a source terminal 2b, a gate terminal 3b and a drain terminal 4b are provided on the insulation layer 9b. Two power MOSFET chips 1a and two power MOSFET chips 1b are mounted on the drain terminals 4a and 4b, respectively. The power MOSFET chips 1a and 1b are fixed on the drain terminals 4a and 4b by connection layers 10a and 10b, respectively, thereby to establish electrical and mechanical connections therebetween. The connection layers 10a and 10b may be layers of solder, brazing filler metal or the like. The gate electrodes 17a of the power MOSFET chips 1a shown in FIG. 1 and FIG. 2 are electrically connected to the gate terminal 3a by gate wires 7a. On the other hand, the source electrodes 19a of the power MOSFET chips 1a shown in FIG. 1 and FIG. 2 are electrically connected to the source terminals 2 by bounding wires 8a. Although the location of 17a (17b) and 19a (19b) are not shown in FIG. 3, they form part of the top layer of chip 1a (1b) including the points to which wires 8a (8b) are connected. A connecting structure for the power MOSFET chip 1b is similar to that for the power MOSFET chip 1a. Namely, the gate electrodes 17b and the source electrodes 19b are connected to the gate terminal 3b and the source terminal 2b by bonding wires 7b and 8b, respectively.
FIG. 5 is an equivalent circuit diagram of the MOSFET element. A diode 21 shown in FIG. 5 is constructed by a PN junction structure consisting of the N.sup.- -type layer 13a (13b) and the P.sup.+ -type region 14a (14b), each of which is shown in FIG. 2. An N-channel MOSFET 24 is constructed by an NPN junction structure consisting of the N.sup.+ -type region 15a (15b), the P.sup.+ -type region 14a (14b) and the N.sup.- -type layer 13a (13b), each of which is shown in FIG. 2.
FIG. 6 shows an equivalent circuit of the semiconductor device of FIG. 3. A circuit 22 corresponds to an equivalent circuit of the power MOSFET chips 1a shown in FIG. 3. Since each power MOSFET chip 1a is constructed by interconnecting the MOSFET elements of FIG. 5 in parallel, the circuit 22 expressing the equivalent circuit of the power MOSFET chips 1a is identical to that of the MOSFET elements shown FIG. 5. Similarily, a circuit 23 expresses an equivalent circuit of the power MOSFET chips 1b shown in FIG. 3.
After the wire bonding processes, a case 6 of epoxy resin or the like is fixed to the substrate 5, thereby to complete the assembly of the semiconductor device.
In the semiconductor device constructed as above, the following operation characters are required: First is a high speed switching character, the second is a high voltage-proof and a large current capacity, and the third is a low power loss in a switching operation.
Usually, a current of several ten to one hundred amperes flows in a semiconductor device, and an electrode structure capable of such a current is required. In a prior art, the requirement is satisfied by increasing the source wires 8a and 8b in number so that a current density in each source wire is decreased. For example, the device shown in FIG. 3 has three source wires for each power MOSFET chip.
Recently, however, the number of wires is increased according to an increase of a control current, thereby to cause the following problems:
(1) Since the intrinsic inductance of the source wire cannot be ignored, the switching speed decreases.
(2) A contact resistance in bonding structure is increased, and therefore, a power loss caused in the bonding structure is increased.
(3) A mass productivity of the semiconductor device is deteriorated, since the bonding process becomes to be complicated.
Further, since a size of the semiconductor device comprising the MOSFET chip is larger than that of other semiconductor devices such as a dynamic random access memory, the bonding wires used in the former should be longer than those used in the latter. As a result, the electric resistance of the source wires employed in the semiconductor device comprising the MOSFET chip increases, and therefore, a power loss in the source wires also increases.